This invention is in the field of integrated circuit electrical testing. Embodiments of this invention are more specifically directed to the screening of integrated circuits including ferroelectric cells that are potentially of weak long term reliability.
Conventional metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) logic and memory devices are prevalent in modern electronic systems, as they provide an excellent combination of fast switching times and low power dissipation, along with their high density and suitability for large-scale integration. As is fundamental in the art, however, those devices are essentially volatile, in that logic and memory circuits constructed according to these technologies do not retain their data states upon removal of bias power. Especially in mobile and miniature systems, the ability to store memory and logic states in a non-volatile fashion is very desirable. As a result, various technologies for constructing non-volatile devices have been developed in recent years.
A recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead zirconate titanate (PZT) or strontium-bismuth-tantalate (SBT), rather than silicon dioxide or silicon nitride as typically used in non-ferroelectric capacitors. Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors. In contrast, conventional MOS capacitors lose their stored charge on power-down of the device. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits, for example placing capacitors above the transistor level, between overlying levels of metal conductors.
Ferroelectric technology is now utilized in non-volatile solid-state read/write random access memory (RAM) devices. These memory devices, commonly referred to as “ferroelectric RAM”, or “FeRAM”, or “FRAM” devices, are now commonplace in many electronic systems, particularly portable electronic devices and systems. FRAMs are especially attractive in implantable medical devices, such as pacemakers and defibrillators. Various memory cell architectures including ferroelectric capacitors are known in the art, including the well-known 2T-2C (two transistor, two capacitor) cells in which the two ferroelectric capacitors in a cell are polarized to complementary states. Another type of FRAM cell is based on the well-known “6T” CMOS static RAM cell, which operates as an SRAM cell during normal operation, but in which ferroelectric capacitors coupled to each storage node can be programmed with the stored data state to preserve memory contents in non-volatile fashion. Ferroelectric capacitors are also implemented in some integrated circuits as programmable analog capacitors. Ferroelectric cells constructed in a 1T-1C (one transistor, one capacitor) arrangement, similar to conventional dynamic RAM memory cells, are attractive because of their small chip area, but at a cost of less robust read performance than the latching but larger area 2T-2C and 6T cell types.
FIG. 1a illustrates an example of a Q-V characteristic of a conventional ferroelectric capacitor. As shown, the charge (Q) stored across the conductive plates depends on the voltage applied to the plates (V), and also on the recent history of that voltage. If the voltage V applied across the capacitor plates exceeds a “coercive” voltage +Vα, the capacitor polarizes into the “+1” state. According to this characteristic, once polarized to the “+1” state, so long as voltage V remains above coercive voltage −Vβ, the capacitor exhibits a stored charge of +Q1. Conversely, if the voltage V applied across the capacitor plates is more negative than coercive voltage −Vβ, the capacitor is polarized into the “−1” state, and will exhibit a stored charge of −Q2 for applied voltage V below +Vα.
An important characteristic of ferroelectric capacitors, for purposes of non-volatile storage in integrated circuits, is the difference in capacitance exhibited by a ferroelectric capacitor between its polarized states. As fundamental in the art, the capacitance of an element refers to the ratio of stored charge to applied voltage. While the ferroelectric capacitor has a linear capacitance, by virtue of its construction as parallel plates separated by a dielectric film (i.e., the ferroelectric material), it also exhibits significant polarization capacitance (i.e., charge storage) in response to changes in polarization state that occurs upon application of a polarizing voltage. For example, referring to FIG. 1a, the polarization of a ferroelectric capacitor from its “−1” state to its “+1” state is reflected in a relatively high capacitance C(−1), reflecting the storage of polarization charge in the capacitor in response to the change of polarization state by the voltage exceeding coercive voltage Vα. On the other hand, a capacitor that already in its “+1” state exhibits little capacitance C(+1) due to polarization, since its ferroelectric domains are already aligned in the direction of the applied coercive voltage, causing little additional polarization charge to be stored. As will be evident from the following description, a stored logic state is read by interrogating the capacitance of the ferroelectric capacitors to discern its polarization state.
By way of further background, it has been observed that the polarization properties of conventional ferroelectric capacitors are quite sensitive to the presence of hydrogen. More specifically, the infiltration of hydrogen into the ferroelectric film is believed to cause degradation in the hysteresis characteristic of the ferroelectric capacitor. In FRAM memory applications, this degradation is exhibited by weakened data retention, also referred to as “imprint degradation”, particularly for the “−1” polarization state according to the nomenclature of FIG. 1a. 
FIG. 1b illustrates, in cross-section, a typical construction of a portion of an integrated circuit including a ferroelectric capacitor and an n-channel metal-oxide-semiconductor (MOS) transistor. In this arrangement, a MOS transistor is realized at the surface of p-type substrate 10 (or well), at an active region disposed between isolation dielectric structures 15 formed by shallow trench isolation in this example. N+ source/drain regions 14 are formed into substrate 10 on opposing sides of polysilicon gate element 16 in a self-aligned manner. Gate element 16 is separated from the surface of the active region by gate dielectric 17, thus forming the transistor. Sidewall spacers 19 are provided on the sides of gate element 16 as useful in forming source/drain region extensions, as known in the art. A ferroelectric capacitor is formed in this structure by a ferroelectric stack including conductive plates 20a, 20b (formed of an elemental metal, or a conductive metal compound such as a metal nitride, conductive metal oxide, or a silicide, or a stack of two or more of these layers) between which ferroelectric material 22 is disposed. In this example, ferroelectric material 22 consists of PZT. Bottom conductive plate 20a is connected to the source/drain region 14 by conductive plug 18 formed into a contact opening etched through dielectric film 13.
Conventional process flows for manufacturing ferroelectric capacitors such as shown in FIG. 1b have addressed the issue of hydrogen contamination of the ferroelectric material by depositing passivation films over the ferroelectric capacitor structure. For example, referring to FIG. 1b, multiple passivation films are formed over the ferroelectric stack to inhibit hydrogen contamination of ferroelectric material 22. In this conventional example, aluminum oxide layer 24 is formed over the ferroelectric stack, for example to a thickness of about 25 nm, and serves both as a hydrogen barrier and also as a chemical barrier between ferroelectric material 22 and the other passivation films. Silicon nitride layer 25 is formed over aluminum oxide layer 24, for example to a thickness of about 50 nm, by high-density plasma (HDP), followed by a second silicon nitride film 26, deposited by chemical vapor deposition (CVD) to a thickness (e.g., about 50 nm) sufficient to fill any gaps or thin spots (i.e., voids) in HDP nitride 25, and which increases the thickness of the overall passivation layer. However, long-term reliability testing shows that some portion of the population of integrated circuits including FRAM cells remain vulnerable to depolarization over time, despite this passivation.